The present invention relates to integrated circuits, and more particularly, to hybrid nanowire field effect transistor (FET) and FinFET devices and methods for fabrication thereof.
Complementary metal-oxide semiconductor (CMOS) circuits typically include a combination of n-type and p-type field effect transistor (FET) devices. Each FET device includes a source, a drain and a channel between the source and the drain. A gate electrode over and/or surrounding the channel regulates electron flow between the source and the drain.
As feature sizes of CMOS circuits get increasingly smaller (commensurate with current technology) a number of challenges arise. For instance, scaling brings about issues related to electrostatics and mobility degradation in CMOS devices. A finFET architecture offers increased scaling opportunities beyond that attainable with planar devices. FinFET devices exhibit fast switching times and high current densities.